1. Field of the Invention
The present invention relates to a method for producing thin dice from fragile materials such as semiconductor materials, quartz, sapphire, ceramics, etc.
2. Description of the Related Art
There are several reasons for producing thin chips or dice out of fragile materials. A thin die is a die having a thickness of 4 mils (0.004 inches) or less, and fragile materials include semiconductor materials, quartz, sapphire, ceramics, etc. Thin chips have lower thermal impedances than their thicker counter-parts, an important factor in high power applications. Additionally, thin dice encounter less stress due to mismatches in thermal coefficients of expansion. Thin dice also allow for thinner packaging. Accordingly, thin semiconductor dice simplify the manufacture of "Smart-Cards." Besides Smart-Cards, a demand for thin dice exists in applications such as high power microprocessors, optical sensors, ultra-thin semiconductor packages, crystal oscillators, magnetic heads for disc drives, microwave transistors, etc.
Several different methods exist for forming thin semiconductor dice. Typically, a semiconductor wafer having devices formed thereon is thinned by grinding, and then the thin wafer is diced. U.S. Pat. No. 5,268,065 to Grupen-Shemansky discloses such a method for producing thin semiconductor dice. Several problems arise when dicing a thin wafer. The dicing is performed by making saw cuts along the wafer between the semiconductor devices to form semiconductor dice or chips. When making saw cuts on a thin semiconductor wafer, however, chip outs can occur. Other problems such as wafer or die cracking and ragged chip edges are encountered when making saw cuts along a thin wafer. To reduce the occurrence of chip outs and other problems, the speed with which the saw cuts are made must be reduced to 0.25 inches per second or less. Even then, however, chip outs, ragged edges, and wafer or die cracking may occur. By contrast, these problems do not arise when making saw cuts in a semiconductor wafer of normal thickness.
U.S. Pat. No. 5,071,792 to VanVonno discloses another process for forming thin semiconductor dice. In the VanVonno process, grooves are formed in the semiconductor wafer, and these grooves are filled with a grind resistant material such as silicon nitride. VanVonno inverts the wafer and fixes the grooved surface of the wafer to a substrate using wax. VanVonno then grinds the semiconductor surface opposite the grooves until reaching the grind resistant material. The grind resistant material is then etched away. VanVonno then melts the wax to obtain the individual semiconductor dice. Unfortunately, the individual dice move during the wax melting process destroying the known position and alignment of the dice. This, consequently, makes further handling and processing of the dice extremely difficult.
U.S. Pat. No. 5,275,958 to Ishikawa discloses a method for producing semiconductor chips. In Ishikawa grooves are formed in a first surface of the semiconductor wafer, and metal is deposited in the grooves. The wafer is then inverted, and grooves, matching the groove pattern formed in the first surface, are formed in a second surface of the wafer opposite the first surface. The grooves in the second surface expose the metal deposited in the grooves of the first surface. Ishikawa then deposits metal in the grooves formed in the second surface. Dicing is carried out by cutting the metal which joins the individual dice. Consequently, sections of ragged metal line the chip edges.
U.S. Pat. No. 5,273,940 to Sanders discloses a method of forming a multiple chip package with thinned semiconductor chips. In Sanders, a plurality of chips are mounted to a substrate, semiconductor device side down. An encapsulation material is placed on the surface of the substrate to protect the surface from exposure to the external environment. Sanders then thins the semiconductor chips by grinding the exposed surface of the semiconductor chips.
U.S. Pat. No. 5,302,554 to Kashiwa discloses a method of producing thin semiconductor chips. In Kashiwa, grooves are formed in a semiconductor wafer. Kashiwa then grinds the surface opposite the grooves to reduce the thickness of the semiconductor wafer. The grooves, however, are not exposed. A plated heat sink layer is then formed on the ground surface of the semiconductor wafer, and individual heat sinks are formed on the plated heat sink layer corresponding to the individual dice. A dicing tape is then applied to the individual heat sinks, and the semiconductor wafer is diced along the grooves.
U.S. Pat. No. 5,324,687 to Wojnarowski discloses a method for thinning integrated circuit chips for lightweight packaged electronic systems. In Wojnarowski, individual dice are placed into pockets formed in a substrate. Wojnarowski then applies an adhesive layer over the surface of the substrate having the pockets formed therein. Wojnarowski then grinds the surface of the substrate opposite the surface having the pockets formed therein. During grinding, enough substrate is removed to expose the individual dice in their respective pockets. Grinding continues to thin the individual dice.
Each of the methods discussed above either dices a thin semiconductor wafer, requires handling of individual dice prior to thinning, or requires a complex series of processing steps to form thin semiconductor dice.